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Weltrend Semiconductor, Inc.
WT6805
Monitor On-Screen Display
Preliminary Data Sheet
REV. 1.1 August 30, 2002
The information in this document is subject to change without notice. Weltrend Semiconductor, Inc. All Rights Reserved.
24 2 2F, No. 24, Industry E. 9th RD., Science-Based Industrial Park, Hsin-Chu, Taiwan TEL:886-3-5780241 FAX:886-3-5794278.5770419 Email:support@weltrend.com.tw www..com
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GENERAL DESCRIPTION
WT6805
Data Sheet Rev. 1.1
The WT6805 is an on-screen display (OSD) IC which display color symbols or characters onto monitor. With the control of microcontroller through I2C interface, it can display characters with special effect like blinking or shadowing automatically.
FEATURES
* * * * * * * * * * * * * * * * * * * * Programmable horizontal resolutions up to 1530 dots per line Horizontal frequency up to 150KHz On-chip PLL up to 150MHz Fully programmable character array of 15 rows by 30 columns 12x18 dot matrix per character 512 characters and graphic symbols ROM 16 multi-color fonts 8 user RAM font 8 colors per display character 7 colors per display character background 4 programmable windows Double character height and width control Programmable character height (18 to 71 lines) Programmable row-to-row spacing Programmable vertical and horizontal positioning for display screen center Bordering, shadowing, blinking and box effect Fade-in/fade-out effects I2C interface with slave address $7AH Power supply : 5V Package type : 16-pin plastic DIP/SOP
PIN ASSIGNMENT AND PACKAGE TYPE
PACKAGE TYPE : PDIP-16, SOP-16
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Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name VSSA RV VCO VDDA HFLB CLKIN SDA SCL VDD VFLB POUT FBKG BOUT GOUT ROUT VSS I O O O O O I I I/O I I I/O I/O Analog ground. Description
WT6805
Data Sheet Rev. 1.1
A resistor can be connected to this pin for control VCO range. Loop filter of PLL. Analog power supply Horizontal sync input. External clock input. Serial data of I2C interface. Serial clock of I2C interface. Digital power supply Vertical sync input. General purpose output pad Fast Blanking output. This pin controls the mixer of vedio amplifier to cutoff the video signal while displaying character or window. Blue color output Green color output Red color output Digital ground
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FUNCTIONAL DESCRIPTION
I2C Interface
This is a slave mode I2C interface. Device address is $7AH. There are three data transmission formats for writing: Format (a), (b) and (c). Format (a):
S 01111010 A ROW A COL A Data A ROW A COL A
WT6805
Data Sheet Rev. 1.1
Data
A
*****
P
Format (b):
S 01111010 A ROW A COL A Data A COL A Data A COL A
*****
P
Format (c):
S 01111010 A ROW A COL A Data A Data A Data A Data A
*****
P
Where S = START condition R/W = Read/Write control bit. "1" means READ operation and "0" means WRITE operation. A = Acknowledge bit. "0" means acknowledge. P = STOP condition ROW = Row address byte COL = Column address byte Data = Data byte Format (a) is used when write data in different row and column address. Format (b) is used when write data in the same row. Format (c) is suitable for writing data sequentially. The column address will increase automatically. Format (a)(b), Format (a)(c), Format (b)(a) or Format (b)(c) is allowed. But Format (c)(a) and Format (c)(b) is not allowed.
Device Adrees Match (111)
0,X
Idle (100)
Input=bit7,bit6
1,X 1,X
0,1 Format (c)
ROW (000)
0,0
Format (a) COL c
(001)
COL ab
(010)
1,X X,X X,X DATA c
(011)
Format (b) X,X 0,0
0,1
DATA ab
(110)
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Transmission Format Address Row Address Bytes Columna,b in Display RAM (Row0~14) Columnc Data Row Attribute Bytes Columna,b in Display RAM Columnc Data Row Columna,b Columnc Data
WT6805
Data Sheet Rev. 1.1
Bit7 1 0 0 D7 1 0 0 D7 1 0 0 D7 1 0 0 D7
Bit6 0 0 1 D6 0 0 1 D6 1 0 1 D6 0 0 1 D6
Bit5 0 D8 D8 D5 1 x x D5 0 C5 C5 D5 0 X X D5
Bit4 R4 C4 C4 D4 R4 C4 C4 D4 R4 C4 C4 D4 R4 C4 C4 D4
Bit3 R3 C3 C3 D3 R3 C3 C3 D3 R3 C3 C3 D3 R3 C3 C3 D3
Bit2 R2 C2 C2 D2 R2 C2 C2 D2 R2 C2 C2 D2 R2 C2 C2 D2
Bit1 R1 C1 C1 D1 R1 C1 C1 D1 R1 C1 C1 D1 R1 C1 C1 D1
Bit0 R0 C0 C0 D0 R0 C0 C0 D0 R0 C0 C0 D0 R0 C0 C0 D0
Format a,b,c a,b c a,b,c a,b,c a,b c a,b,c a,b,c a,b c a,b,c a,b,c a,b c a,b,c
User Fonts
Row Control Columna,b Registers (Row15~16) Columnc Data
There are two ways to change D8 in format (c) of Row0~Row14 address byte. - write D8 with column address. - If the TP bit in Row16 Column3 is "1", use data byte $FFh to toggle D8. This function can toggle D8 without restarting a new I2C command. However, the fonts located at $0FFh and $1FFh cannot be displayed in this condition. Example: If TP bit is set, write "S - 7A - 81 - 60 - 58 - 54 - FF- 07 - 09 - 01 - 06 - P" The operation is : (Row1, Column0) <= $158h (Row1, Column1) <= $154h Toggle D8 (Row1, Column2) <= $007h (Row1, Column3) <= $009h (Row1, Column4) <= $001h (Row1, Column5) <= $006h
The read format is shown as follow.
S 01111010 A ROW A COL A S 01111011 A Data A Data A
*****
P
Must use write format first to set row and column address, then follows a read command.
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Display RAM and Row Control Register
DISPLAY RAM
WT6805
Data Sheet Rev. 1.1
The display RAM stores the data to be displayed. Address byte determines display character and attribute bytes determines character background, character color and blinking effect. The memory location is shown as below. 0 0
CLOLUMN
29 30
31 0
R O W
14
CHARACTER Address
ROW Control Reserved Register
14
0 0
CLOLUMN
29 30
31 0
R O W
14
CHARACTER Attribute
Reserved Reserved
14
Address Byte
(Row,Col) R/W Bit 8 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
( 0, 0) : (14,29) CA8~CA0 -
W
CA8
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
9-bit address of Character ROM.
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Attribute Byte
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2
WT6805
Data Sheet Rev. 1.1
Bit 1
Bit 0
( 0, 0) : (14,29)
W
--
BG_R/ BOX2
BG_G/ BOX1
BG_B/ BOX0
BLINK
CH_R
CH_G
CH_B
BG_R, BG_G, BG_B - Background color of its corresponding character. BG_R 0 0 0 0 1 1 1 1 BG_G 0 0 1 1 0 0 1 1 BG_B 0 1 0 1 0 1 0 1 Color Background Blue Green Cyan Red Magenta Yellow White
BOX2,BOX1,BOX0 - Character button box format selection of its relative character BOX2 0 0 0 0 1 1 1 1 BOX1 0 0 1 1 0 0 1 1 BOX0 0 1 0 1 0 1 0 1 Function Disabled button box. End of button box. Middle of button box. Reserved. Start depressed button box. More than one character. Start depressed button box. One character only. Start raised button box. More than one character. Start raised button box. One character only.
BLINK - Enable blinking effect of its corresponding character. The blinking speed is controlled by BNK1 and BNK0 bits. CH_R, CH_G, CH_B - Color of its corresponding character. CH_R 0 0 0 0 1 1 1 1 CH_G 0 0 1 1 0 0 1 1 CH_B 0 1 0 1 0 1 0 1 Color Black Blue Green Cyan Red Magenta Yellow White
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WT6805
Data Sheet Rev. 1.1
Example of button box
(BOX2-BOX0)=
( 1, 1, 1)
( 1, 1, 0)
( 0, 1, 0)
( 0, 0, 1)
(BOX2-BOX0)=
( 1, 0, 1)
( 1, 0, 0)
( 0, 1, 0)
( 0, 0, 1)
ROW Control Register
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
( 0,30) : (14,30)
W
--
--
--
BOX
--
--
DCH
DCW
BOX - "0" : Background color attribute bits (BG_R, BG_G, BG_B) are used. "1" : Button boxes bits (BOX2, BOX1, BOX0) are used. DCH - Double Character height DCW - Double Character width. The character width of even column (column 0, 2, 4, 6, ....) is doubled and the odd column will not display. Write data into RAM must enable PLL or external clock. The I2C interface clock frequency must less than 1/24 pixel clock frequency.
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User Fonts RAM
WT6805
Data Sheet Rev. 1.1
There are 8 user fonts can be stored in the RAM. The RAM structure is shown below. Each font occupies one Row. Column # Row # 0 1 2 3 4 5 6 7 0123456 34 35 36 37 63
User Fonts RAM
Reserved
The data structure of RAM font is shown below.
Column# 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 Data 00h 00h 02h 06h 0Eh 1Eh 06h 06h 06h 06h 06h 06h 06h 1Fh 1Fh 00h 00h 00h Column# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 Data 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 80h 80h 00h 00h 00h
Line0 Line1 Line2 Line3 Line4 Line5 Line6 Line7 Line8 Line9 Line10 Line11 Line12 Line13 Line14 Line15 Line16 Line17
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Window Control
WT6805
Data Sheet Rev. 1.1
Window 1 has the highest priority and window 4 is the least. If window overlapping occurs, the higher priority covers the lower and the higher priority color will take over on the overlap window area. Window 1 Control Registers
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
(15,0) (15,1) (15,2)
W W W
W1RS3 W1CS4 W1CE4
W1RS2 W1CS3 W1CE3
W1RS1 W1CS2 W1CE2
W1RS0 W1CS1 W1CE1
W1RE3 W1CS0 W1CE0
W1RE2 W1EN W1_R
W1RE1 -W1_G
W1RE0 W1SHD W1_B
W1RS3~0 - Window 1 Row start address W1RE3~0 - Window 1 Row end address W1CS4~0 - Window 1 Column start address W1CE4~0 - Window 1 Column end address W1EN - Enable Window 1. Default value = 0 W1SHD - Enable the shadow effect of the window 1. Default value = 0 W1_R, W1_G, W1_B - Define the color of window 1 W1_R W1_G W1_B Color 0 0 0 Black 0 0 1 Blue 0 1 0 Green 0 1 1 Cyan 1 0 0 Red 1 0 1 Magenta 1 1 0 Yellow 1 1 1 White
Window 2 Control Registers
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
(15,3) (15,4) (15,5)
W W W
W2RS3 W2CS4 W2CE4
W2RS2 W2CS3 W2CE3
W2RS1 W2CS2 W2CE2
W2RS0 W2CS1 W2CE1
W2RE3 W2CS0 W2CE0
W2RE2 W2EN W2_R
W2RE1 -W2_G
W2RE0 W2SHD W2_B
Window 3 Control Registers
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
(15,6) (15,7) (15,8)
W W W
W3RS3 W3CS4 W3CE4
W3RS2 W3CS3 W3CE3
W3RS1 W3CS2 W3CE2
W3RS0 W3CS1 W3CE1
W3RE3 W3CS0 W3CE0
W3RE2 W3EN W3_R
W3RE1 -W3_G
W3RE0 W3SHD W3_B
Window 4 Control Registers
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
(15,9) (15,10) (15,11)
W W W
W4RS3 W4CS4 W4CE4
W4RS2 W4CS3 W4CE3
W4RS1 W4CS2 W4CE2
W4RS0 W4CS1 W4CE1
W4RE3 W4CS0 W4CE0
W4RE2 W4EN W4_R
W4RE1 -W4_G
W4RE0 W4SHD W4_B
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Frame Control Register
OSD Vertical Starting Position Register This register controls the vertical displacement from top.
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2
WT6805
Data Sheet Rev. 1.1
Bit 1
Bit 0
(15,12)
W
VS7
VS6
VS5
VS4
VS3
VS2
VS1
VS0
Default Value = $04h Minimum value = $01h VS7~VS0 - Vertical starting position. Each step is 4 Horizontal lines. Vertical starting position = (VS x 4 )+2 VFLB R,G,B Output
VS
OSD Horizontal Starting Position Register This register controls the vertical displacement from top.
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
(15,13)
W
HS7
HS6
HS5
HS4
HS3
HS2
HS1
HS0
Default Value = $0Fh Minimum value = $01h HS7~HS0 - Horizontal starting position. Each step is 6 dots. Horizontal starting position = (HS x 6) + 45 dot + PLL phase error HFLB R,G,B Output
HS
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Character Height Enlargement Register
WT6805
Data Sheet Rev. 1.1
This register enlarges the character height. The enlargement is done by repeating lines of every row.
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
(15,14)
W
--
CH6
CH5
CH4
CH3
CH2
CH1
CH0
Default Value = $00h CH6~CH0 - Define the enlargement of character height.
CH6 CH5 CH4 CH3 CH2 CH1 CH0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 x 0 0 0 0 0 0 1 1 0 1 0 1 1 x 0 0 0 0 1 1 0 0 0 0 0 0 0 x 0 0 0 1 0 1 0 0 0 0 0 0 0 x 0 0 1 0 0 1 0 0 0 0 0 0 0 x 0 1 0 0 0 1 0 1 0 1 0 0 1 Total Lines 18 18 19 20 22 26 33 34 35 36 53 54 70 71
Repeat Line
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v
v v
v v v
v
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Horizontal Resolution Register
WT6805
Data Sheet Rev. 1.1
This register controls the pixel clock frequency which is multiplied by HFLB input.
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
(15,15)
W
--
HR6
HR5
HR4
HR3
HR2
HR1
HR0
Default Value = $40h HR6~HR0 - Define the Horizontal resolution (i.e. pixels per horizontal line). Dot frequency = {(HR[6:0]x2) + HORR}x 6 x fHFLB where HORR is the bit0 of (Row16, Column 3) register Row-to-Row Spacing Register This register controls the row-to-row spacing. It adds line(s) below each row.
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
(15,16)
W
--
--
--
RSP4
RSP3
RSP2
RSP1
RSP0
Default Value = $00h RSP4~RSP0 - Define the line(s) below each row. Display Control Register
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
(15,17)
W
ENOSD
BSEN
SHADW
FADE
BLEND
WINCLR RAMCLR FBKGC
Default Value = $00h ENOSD - Enable OSD Display. BSEN - Enable bordering and shadowing effect SHADW - "1" : Shadowing. "0" : Bordering FADE - Fade in /Fade out Enable BLEND - Blending in/out select when FADE bit is set. WINCLR - Clear all window enable bits. (W1EN ~ W4EN) RAMCLR - Clear all ADDRESS bytes, BG_R, BG_G, BG_B and BLINK bits. FBKGC - FBKG control. "0" : FBKG pin outputs during displaying character or window "1" : FBKG pin outputs during displaying character only.
Normal
Shadow
Border
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Output Control Register
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2
WT6805
Data Sheet Rev. 1.1
Bit 1
Bit 0
(15,18)
W
TRIC
FSS
--
SELVCL
HPOL
VPOL
VC1
VC0
Default Value = $FCh TRIC - Tri-state control of ROUT, GOUT, BOUT and FBKG pin. "1" - When OSD is disabled, these pins will drive low. "0" - When OSD is disabled, these pins will be in high impedance state FSS - Font size select. "0" - 12x16 font size. "1" - 12x18 font size. SELVCL - Auto synchronize Hsync with Vsync. "0" - Disable. "1" - Enable. HPOL - "1": Accept positive polarity of Hsync input. "0" : Accept negative polarity of Hsync input. VPOL - "1": Accept positive polarity of Vsync input. "0" : Accept negative polarity of Vsync input. VC1,VC0 - VCO control The VCO range is depend on the resistor on Pin2. When Pin2 connect a 6.2K resistor to ground, the VCO range is shown below. VC1 0 0 1 1 VC0 0 1 0 1 Frequency range 12MHz ~ 28MHz 28MHz ~ 56MHz 56MHz ~ 112MHz 112MHz ~ 150MHz
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Shadow and Border Effect
Shadow Color Register
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2
WT6805
Data Sheet Rev. 1.1
Bit 1
Bit 0
(15,19)
W
--
--
--
--
--
CS_R
CS_G
CS_B
Default Value = $00h CS_R, CS_G, CS_B - Define the color of character shadow or border CS_R 0 0 0 0 1 1 1 1 CS_G 0 0 1 1 0 0 1 1 CS_B 0 1 0 1 0 1 0 1 Color Black Blue Green Cyan Red Magenta Yellow White
Full Screen test pattern control register
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
(15,20)
W
FSW
--
--
--
--
FSR
FSG
FSB
Default Value = $00h FSW - Enable full screen test pattern when this bit is set. FBKG pin is forced to high to video FSR,FSG,FSB - Define the color of full screen test pattern. FSR 0 0 0 0 1 1 1 1 FSG 0 0 1 1 0 0 1 1 FSB 0 1 0 1 0 1 0 1 Color Black Blue Green Cyan Red Magenta Yellow White
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Window Shadow Width Register This register controls the width of window shadow.
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2
WT6805
Data Sheet Rev. 1.1
Bit 1
Bit 0
(15,21)
W
WSW41
WSW40
WSW31
WSW30
WSW21
WSW20
WSW11
WSW10
Default Value = $00h WSW41,WSW40 - Shadow width of Window 4. WSW31,WSW30 - Shadow width of Window 3. WSW21,WSW20 - Shadow width of Window 2. WSW11,WSW10 - Shadow width of Window 1. Width = (bit value x 2) + 2 dots Window Shadow Height Register This register controls the height of window shadow.
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
(15,22)
W
WSH41
WSH40
WSH31
WSH30
WSH21
WSH20
WSH11
WSH10
Default Value = $00h WSH41,WSH40 - Shadow height of Window 4. WSH31,WSH30 - Shadow height of Window 3. WSH21,WSH20 - Shadow height of Window 2. WSH11,WSH10 - Shadow height of Window 1. Height = (bit value x 2) + 2 lines
Window Shadow Height
Window Shadow Width
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Window Shadow Color Register
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2
WT6805
Data Sheet Rev. 1.1
Bit 1
Bit 0
(16,0) (16,1)
W W
---
W1SR W3SR
W1SG W3SG
W1SB W3SB
---
W2SR W3SR
W2SG W3SG
W2SB W3SB
Default Value = $00h W1SR, W1SG, W1SB - Define the shadow color of window 1. W2SR, W2SG, W2SB - Define the shadow color of window 2. W3SR, W3SG, W3SB - Define the shadow color of window 3. W4SR, W4SG, W4SB - Define the shadow color of window 4. WnSR 0 0 0 0 1 1 1 1 WnSG 0 0 1 1 0 0 1 1 WnSB 0 1 0 1 0 1 0 1 Color Black Blue Green Cyan Red Magenta Yellow White
Multi-color Font Selection Register
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
(16,2)
W
--
--
--
--
--
--
UFONT
CFONT
Default Value = $01h UFONT - "1" : Enable user font. Address $1E8h~$1EFh is user font. "0" : Disable multi-color font. Address $1E8h~$1EFh is single color font. CFONT - "1" : Enable multi-color font. Address $1F0h~$1FFh is multi-color font. "0" : Disable multi-color font. Address $1F0h~$1FFh is single color font.
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Fade in/Fade out Effect
WT6805
Data Sheet Rev. 1.1
The fade-in/fade-out effect can be controlled either in horizontal direction only, vertical direction only or both direction. Fade in/out Control Register
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
(16,3)
W
DISH
DISV
FVC1
FVC0
BKS1
BKS0
TP
HORR
Default Value = $00h DISH : Disable fade in/out horizontal direction. Increment/decrement one column per frame. DISV : Disable fade in/out vertical direction FVC1,FVC0 : Fade in/out vertical speed control 00 - When BLEND=0, increment/decrement 1 row per frame. When BLEND=1, it take 32 frames to finish blending effect 01 -When BLEND=0, increment/decrement 1 row every two frame When BLEND=1, it take 40 frames to finish blending effect 10 -When BLEND=0, increment/decrement 1 row every three frame When BLEND=1, it take 48 frames to finish blending effect 11 -When BLEND=0, increment/decrement 1 row every four frame When BLEND=1, it take 56 frames to finish blending effect BKS1,BKS0 : Blinking speed select 00 - 32 frames on, 32 frames off 01 - 40 frames on, 40 frames off 10 - 48 frames on, 48 frames off 11 - 56 frames on, 56 frames off TP : Toggle page of character ROM. "0" : D8 is not toggled when display RAM address data byte is $FFh of format (c) "1" : $FFH can toggle D8. This effects only in display RAM address of format (c) and Row0~Row14. HORR : Extension bit of horizontal resolution. Please refer Horizontal Resolution Register.
POUT pin Control
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
(16,4)
W
POC
--
--
--
PO
--
--
--
Default =00h
POC: POUT pin output control. "0" : POUT pin is tri-state. "1" : POUT pin is output. PO: POUT pin output level when POC bit is "1". "0" : POUT pin outputs low. "1" : POUT pin outputs high.
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Clock Source Selection Register
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2
WT6805
Data Sheet Rev. 1.1
Bit 1
Bit 0
(16,5)
W
ENPLL
CLKS
LCD
VREN
CPL
CD2
CD1
CD0
Default Value = $90h ENPLL - "1" : Enable PLL. "0" : Disable PLL. CLKS - Clock select. "0" : Pixel clock comes from PLL. "1" : Pixel clock comes from CLKIN pin, i.e. use external clock. This function is for LCD monitor. LCD - LCD or CRT monitor application select. "0" : For CRT monitor. "1" : For LCD monitor. VREN - VCO resistor enable. "0" : Turn off internal resistor. "1" : Turn on internal resistor. CPL - Control the polarity of CLKIN pin. If CPL=0, no change of CLKIN polarity. If CPL=1, reverse the polarity of CLKIN. CD2~CD0 - When CLKS=1, CD2~CD0 select the pixel clock delay time from CLKIN pin. CD[2:0] 000 001 010 011 100 101 110 111 Delay Time No delay. Delay 2ns. Delay 4ns. Delay 6ns. Delay 8ns. Delay 10ns. Delay 12ns. Delay 14ns.
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Reset
There are two reset sources in WT6805. (1) Low VDD reset When VDD lower than 2.6V, a reset will be generated. (2) Software reset Write register(16,31) will reset the IC just like power on reset.
WT6805
Data Sheet Rev. 1.1
Device ID
MCU can identify the ID of WT6805. The ID is $65h when read following register. This function can let MCU know the OSD IC is from Weltrend or not.
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
(15,31)
R
0
1
1
0
0
1
0
1
TEST Mode
This register is for factory test only, Must keep $00h in normal operation.
(Row,Col) R/W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
(15,31)
W
--
--
TEST5
TEST4
TEST3
TEST2
TEST1
TEST0
Default $00h
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Register Map
(Row,Col) R/W Initial Value Bit 7 Bit 6 Bit 5 Bit4 Bit 3
WT6805
Data Sheet Rev. 1.1
Bit 2
Bit 1
Bit 0
(15,0) (15,1) (15,2) (15,3) (15,4) (15,5) (15,6) (15,7) (15,8) (15,9) (15,10) (15,11) (15,12) (15,13) (15,14) (15,15) (15,16) (15,17) (15,18) (15,19) (15,20) (15,21) (15,22) (15,31) (16,0) (16,1) (16,2) (16,3) (16,4) (16,5) (15,31)
W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W R
b'xxxxxxxx W1RS3 b'xxxxx0x0 W1CS4 b'xxxxxxxx W2RS3 b'xxxxx0x0 W2CS4 b'xxxxxxxx W3RS3 b'xxxxx0x0 W3CS4 b'xxxxxxxx W4RS3 b'xxxxx0x0 W4CS4 b'00000100 b'00001111 b'x0000000 b'x0000100 b'xxx00000 VS7 HS7 ----
W1RS2 W1CS3 W2RS2 W2CS3 W3RS2 W3CS3 W4RS2 W4CS3 VS6 HS6 CH6 HR6 -BSEN FSS ---
W1RS1 W1CS2 W2RS1 W2CS2 W3RS1 W3CS2 W4RS1 W4CS2 VS5 HS5 CH5 HR5 --
W1RS0 W1RE3 W1RE2 W1CS1 W1CS0 W1EN W1_R W2EN W2_R W3EN W3_R W4EN W4_R VS2 HS2 CH2 HR2
W1RE1 -W1_G W2RE1 -W2_G W3RE1 -W3_G W4RE1 -W4_G VS1 HS1 CH1 HR1
W1RE0 W1SHD W1_B W2RE0 W2SHD W2_B W3RE0 W3SHD W3_B W4RE0 W4SHD W4_B VS0 HS0 CH0 HR0
b'xxxxxxxx W1CE4 W1CE3 W1CE2 W1CE1 W1CE0 W2CS1 W2CS0
W2RS0 W2RE3 W2RE2
b'xxxxxxxx W2CE4 W2CE3 W2CE2 W2CE1 W2CE0 W3CS1 W3CS0
W3RS0 W3RE3 W3RE2
b'xxxxxxxx W3CE4 W3CE3 W3CE2 W3CE1 W3CE0 W4CS1 VS4 HS4 CH4 HR4 RSP4 W4CS0 VS3 HS3 CH3 HR3 RSP3
W4RS0 W4RE3 W4RE2
b'xxxxxxxx W4CE4 W4CE3 W4CE2 W4CE1 W4CE0
b'00000000 ENOSD b'11x11100 b'xxxxx000 b'0xxxx000 TRIC -FSW
RSP2 RSP1 RSP0 WINCL RAMCL SHADW FADE BLEND FBKGC R R -SELVCL HPOL VPOL VCO1 VCO0 ------CS_R FSR CS_G FSG WSH11 TEST1 W2SG W3SG TP -CD1 0 CS_B FSB WSH10 TEST0 W2SB W3SB HORR -CD0 1
b'xxxxxxxx WSW41 WSW40 WSW31 WSW30 WSW21 WSW20 WSW11 WSW10 b'xxxxxxxx WSH41 WSH40 WSH31 WSH30 WSH21 WSH20 b'xx000000 b'x000x000 b'x000x000 b'xxxxxx01 b'000000x0 b'0xxx0xxx b'01100101 ----DISH POC 0 -W1SR W3SR -DISV -CLKS 1 TEST5 W1SG W3SG -FVC1 -LCD 1 TEST4 W1SB W3SB -FVC0 -VREN 0 TEST3 ---BKS1 PO CPL 0 TEST2 W2SR W3SR -BKS0 -CD2 1
UFONT CFONT
b'10010000 ENPLL
Weltrend Semiconductor, Inc.
Page 21
eltrend
Electrical Characteristics
D.C Characteristics (VDD=5.0V5%, Ta=0-70C)
Symbol VDD VIH,I2C VIL,I2C VIH,FLB VIL,FLB VOH VOL IIL IDD ISTB VRESET Parameter Supply Voltage SDA and SCL Input High Voltage SDA and SCL Input Low Voltage HFLB and VFLB Input High Voltage HFLB and VFLB Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Operating Current Standby Current Low VDD reset voltage Condition Min. 4.75 0.7VDD -0.3 2.0 -0.3 4 0 -10 --2.4
WT6805
Data Sheet Rev. 1.1
IOH = -6mA IOL = 6mA 0V Typ. 5 -------TBD 0.1 2.6
Max. Unit 5.25 V VDD+0.3 V 0.3VDD V VDD+0.3 V 0.8 V VDD V 0.4 V 10 A 25 mA 1 2.8 mA V
A.C Characteristics (VDD=5.0V, Ta=0-70C)
R,G,B and FBKG pins Symbol Parameter Condition TRISE Rise time (ROUT,GOUT,BOUT Cload=30pF and FBKG pins) TFALL Fall time (ROUT,GOUT,BOUT Cload=30pF and FBKG pins) FHFLB HFLB Input Frequency FVFLB VFLB Input Frequency FPLL PLL Frequency Min. 10 4 6 Typ. 2 2 Max. 3.5 3.5 150K 2047 150 Units ns ns Hz H lines MHz
Weltrend Semiconductor, Inc.
Page 22
eltrend
I2C Timing
Symbol fSCL tBF tHD,START tSU,START tHIGH,SCL tLOW,SCL tHD,DATA tSU,DATA tRISE,I2C tFALL,I2C tSU,STOP Parameter SCL input clock frequency Bus free time Hold time for START condition Set-up time for START condition SCL clock high time SCL clock low time Hold time for DATA input Hold time for DATA output Set-up time for DATA input Set-up time for DATA output SCL and SDA rise time SCL and SDA fall time Set-up time for STOP condition Min. 0 2 1 1 1 1 0 80 20 100 1
WT6805
Data Sheet Rev. 1.1
Typ. -
Max. 100 1 300 -
Units kHz us us us us us ns ns ns ns us ns us
tBF SDA1 tHD,START SCL1 tSU,STOP tLOW,SCL tHD,DATA tHIGH,SCL tSU,DATA tSU,START tRISE tFALL
Weltrend Semiconductor, Inc.
Page 23
eltrend
TYPICAL APPLICATION CIRCUIT
WT6805
Data Sheet Rev. 1.1
The circuit above is for reference only. Component value may vary in different system application.
Weltrend Semiconductor, Inc.
Page 24
eltrend
PACKAGE OUTLINE
PDIP 16-pin package
Package type16 Pin DIP 300mil
SYMBOLS A A1 A2 B C D E E1 F L
WT6805
Data Sheet Rev. 1.1
MIN 0.015 0.125
NOR
UNITINCH MAX 0.210 0.135
0.735 0.245 0.115 0.335 0
0.130 0.018 0.060 0.755 0.300 BSC 0.250 0.100 0.130 0.355 7
0.775 0.255 0.150 0.375 15
eB
Weltrend Semiconductor, Inc.
Page 25

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